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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Detailed Description
The MAX1473 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 100kbps can be achieved.
The MAX1473 is designed to receive binary ASK data
tion, the MAX1473 can reliably produce an ASK output
for RF input levels up to 0dBm with a modulation depth
of 18dB.
The LC tank filter connected to LNAOUT comprises L3
and C2 (see the Typical Application Circuit). Select L3
and C2 to resonate at the desired RF input frequency.
The resonant frequency is given by:
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
f =
1
2 π L TOTAL × C TOTAL
Voltage Regulator
For operation with a single +3.0V to +3.6V supply volt-
age, connect AVDD, DVDD, and V DD5 to the supply
voltage. For operation with a single +4.5V to +5.5V
supply voltage, connect V DD5 to the supply voltage. An
on-chip voltage regulator drives one of the AVDD pins
to approximately +3.2V. For proper operation, DVDD
and both the AVDD pins must be connected together.
Bypass V DD5 , DVDD, and the pin 7 AVDD pin to AGND
with 0.01μF capacitors, and the pin 2 AVDD pin to
AGND with a 0.1μF capacitor, all placed as close as
possible to the pins.
Low-Noise Amplifier
The LNA is an NMOS cascode amplifier with off-chip
inductive degeneration that achieves approximately
16dB of power gain with a 2.0dB noise figure and an
IIP3 of -12dBm. The gain and noise figure are depen-
dent on both the antenna matching network at the LNA
input and the LC tank network between the LNA output
and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible input impedance
match, such as a typical PCB trace antenna. A nominal
value for this inductor with a 50 ? input impedance is
15nH, but is affected by PCB trace. See the Typical
Operating Characteristics for the relationship between
the inductance and the LNA input impedance.
The AGC circuit monitors the RSSI output. When the
RSSI output reaches 2.05V, which corresponds to an
RF input level of approximately -57dBm, the AGC
switches on the LNA gain reduction resistor. The resis-
tor reduces the LNA gain by 35dB, thereby reducing
the RSSI output by about 500mV. The LNA resumes
high-gain mode when the RSSI level drops back below
1.45V (approximately -65dBm at RF input) for 150ms.
The AGC has a hysteresis of ~8dB. With the AGC func-
Maxim Integrated
where:
L TOTAL = L3 + L PARASITICS
C TOTAL = C2 + C PARASITICS
L PARASITICS and C PARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. These
parasitics at high frequencies cannot be ignored, and
can have a dramatic effect on the tank filter center fre-
quency. Lab experimentation should be done to opti-
mize the center frequency of the tank.
Mixer
A unique feature of the MAX1473 is the integrated
image rejection of the mixer. This device eliminates the
need for a costly front-end SAW filter for most applica-
tions. Advantages of not using a SAW filter are
increased sensitivity, simplified antenna matching, less
board space, and lower cost.
The mixer cell is a pair of double balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz IF from a low-side injected LO (i.e., f LO = f RF -
f IF ). The image-rejection circuit then combines these
signals to achieve a minimum 45dB of image rejection
over the full temperature range. Low-side injection is
required due to the on-chip image rejection architec-
ture. The IF output is driven by a source-follower biased
to create a driving impedance of 330 ? ; this provides a
good match to the off-chip 330 ? ceramic IF filter. The
voltage conversion gain is approximately 13dB when
the mixer is driving a 330 ? load.
The IRSEL pin is a logic input that selects one of the
three possible image-rejection frequencies. When
V IRSEL = 0V, the image rejection is tuned to 315MHz.
V IRSEL = V DD /2 tunes the image rejection to 375MHz,
and when V IRSEL = V DD , the image rejection is tuned to
433MHz. The IRSEL pin is internally set to V DD /2 (image
rejection at 375MHz) when it is left unconnected, there-
by eliminating the need for an external V DD /2 voltage.
9
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